
`include "common_header.verilog"

//  *************************************************************************
//  File : sdpm_algn_gen.v
//  *************************************************************************
//  This program is controlled by a written license agreement.
//  Unauthorized reproduction or use is expressly prohibited. 
//  Copyright (c) 2001-2002-2003-2004 Morethanip
//  An der Steinernen Brueke 1, 85757 Karlsfeld, Germany
//  Designed by Francois Balay
//  info@morethanip.com
//  *************************************************************************
//  Decription : Dual Port Memory
//  Version    : $Id: sdpm_algn_gen.v,v 1.5 2008/01/25 03:45:57 dk Exp $
//  *************************************************************************

module sdpm_algn_gen (

   `ifdef FF_USE_REGS

   reset_wclk,
   reset_rclk,

   `endif

   wad,
   din,
   wclk,
   rclk,  
   wren,
   rad,
   dout);
   
parameter FF_WIDTH = 3'b 100;
parameter DEPTH = 8'b 10000000;
parameter ADDR_WIDTH = 3'b 111;

`ifdef FF_USE_REGS
input   reset_wclk;
input   reset_rclk;
`endif 

input   [ADDR_WIDTH - 1:0] wad; 
input   [FF_WIDTH - 1:0] din; 
input   wclk; 
input   rclk; 
input   wren; 
input   [ADDR_WIDTH - 1:0] rad; 
output  [FF_WIDTH - 1:0] dout;
 
`ifdef FF_USE_REGS

reg     [FF_WIDTH - 1:0] dout; 

integer loop_index; 
reg     [FF_WIDTH - 1:0] dpram [DEPTH - 1:0]; 

always @(posedge wclk or posedge reset_wclk)
   begin
      
      if (reset_wclk == 1'b 1)
      begin
        for (loop_index = 0; loop_index <= DEPTH-1; loop_index = loop_index+1)
        begin
        dpram[loop_index]   <= {(FF_WIDTH){1'b 0}};
        end
      end
      
      else if (wren == 1'b 1)
      begin
      dpram[wad] <= din;
      end      
   
   end

always @(posedge rclk or posedge reset_rclk)
   begin
      if (reset_rclk == 1'b 1)
      begin
      dout <= {(FF_WIDTH){1'b 0}};
      end
      else
      begin
      dout <= dpram[rad];
      end
   end

`else

// memory inferral

wire    [FF_WIDTH - 1:0] dout; 
reg     [FF_WIDTH - 1:0] dpram [DEPTH - 1:0];
reg     [ADDR_WIDTH - 1:0] rad_reg;

always @(posedge wclk)
   begin
   if (wren == 1'b 1)
      begin
      dpram[wad] <= din;
      end
   end

always @(posedge rclk)
   begin   
      rad_reg <= rad;	
   end

assign dout = dpram[rad_reg];	

`endif

endmodule // module sdpm_algn_gen